Output Impedance of Wilson Current Mirror

Class-AB Biasing & Monticelli Biasing

Minimum Current Selector (Not what you may think!) - Interview Question

Effect of the Pole-Zero Doublet on the Settling of OpAmps

Stacking vs Cascoding of Transistors

How do interviews evolve from fresher roles to senior-level roles?

Candid Chat with a Senior Analog Designer working in Texas - Gaurav Sarkar

What does a SoC Designer do? Candid Chat with Munoon Jain.

Candid Chat with a Qualcomm RFIC Designer - Shubham Purohit

Overview of Feedforward and Miller Compensation

Candid Chat with Dr. Razavi's PhD Student - Kshitiz Tyagi

Influence of Negative Feedback on the poles of a circuit

Resistor Design in ICs ; Sheet Resistance

Analog IC Design Manager - Chat w/ Rajasekhar

Things you should know before joining a PhD - Penn State University (PSU)

Trimming in Circuits ; Constant Current from a Voltage Reference

Subthreshold Swing doesn’t obey the Boltzmann Limit!

Gain and Rin Computations ; Analog Interview

Super Source Follower

Candid Chat w/ Google Hardware Engineers

Candid Chat with a B.Tech graduate on the VLSI Industry

ID Mismatch of a Current Mirror

Gain/Gm-Boosting ; Interview Questions

What is dBm? Solved Example.

Loop Gain of Bandgap Core

Core Principle of a Bandgap Voltage Reference ; PTAT ; CTAT

What is a Process Design Kit (PDK)/Process Control Document (PCD)?

Pole Cancellation ; Analog Design Interview Question

Looking into a pair of nodes (not what you think!)

OTA Zero