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31:37
RTL based Memory Verification || How industry standard Testbench is written for Verification
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2K views • 1 year ago
32:29
RTL based Verification || functional verification ||Types of testbench ||Stimulus,driver,DUT,monitor
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1.7K views • 1 year ago
33:06
VLSI Design Flow || specification to GDS2 ||Both FPGA and ASIC design flow || what exactly is GDSII
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1.6K views • 1 year ago
16:40
#38-1 Difference between REG and WIRE in verilog, their physical meaning,How to choose REG and WIRE
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2.4K views • 1 year ago
3:13
FPGA based project || RUBIC cube solver || Project link provided
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834 views • 1 year ago
6:44
Square wave extension digital logic diagram with explanation || interview question
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757 views • 1 year ago
20:59
#19-1 Blocking and Non Blocking assignment in a always Block || very important concept
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4.1K views • 1 year ago
39:12
#41 Hardware implementation of FSM ||understand FSM diagram and how to draw digital circuit from FSM
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2.5K views • 1 year ago
6:52
#18-1 How multiple #0 delays are executed in verilog || zero delay control in verilog
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3.2K views • 1 year ago
7:32
#3-1 Number representation in verilog || Number format in verilog
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8.8K views • 1 year ago
5:27
#2-1 Replicate & Concatenation operator in verilog|| Most used operator in verilog ||very important
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11K views • 1 year ago
52:24
SET UP & HOLD TIME ||it's physical meaning|| it's importance||How it's related to CMOS, Capacitor
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1.2K views • 1 year ago
15:39
Edge Detection Logic||Explanation with digital filter & verilog code || Different clock in same code
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1.7K views • 1 year ago
4:06
#4-1 STRING Data type in verilog || Data type in verilog
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7.2K views • 1 year ago
9:47
#12-1 Use of always@(*) in verilog || combinatioal logic design in verilog || very important concept
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6.9K views • 1 year ago
7:26
#10-1 Difference between GATE level and STRUCTURAL Modelling in verilog || interview question
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7.2K views • 1 year ago
11:32
#31-1 forever vs always vs initial in verilog ||forever in verilog||always, initial ||very important
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2.5K views • 1 year ago
30:14
Difference between VERIFICATION, TESTING & VALIDATION in VLSI Design
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5.4K views • 2 years ago
43:31
VLSI Project || DAC( Digital to Analog Converter) interfacing with FPGA using SPI || SPARTAN 3E
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7.1K views • 2 years ago
42:22
LCD Interfacing with FPGA ||Working verilog code||Working principle is same for Microcontroller also
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8.6K views • 2 years ago
49:01
(Part -3) Digital logic SYNTHESIS || why synthesis || Synthesis flow || Synthesis interview question
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5.5K views • 2 years ago
1:08:12
( Part -2 ) RTL Coding Guidelines || What is RTL || RTL Code = verilog code + RTL coding guidelines
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15K views • 2 years ago
1:08:20
VLSI Project || RF based WIRELESS data transmission between two FPGA ||SPI || NRF24L01||Verilog Code
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4.7K views • 2 years ago
25:23
( Part -1 ) SPEC in VLSI Design|| Datasheet for chip designing || Frontend Design flow
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4.7K views • 2 years ago
1:35:43
I2C protocol with Verilog code || Onboard I2C controlled EEPROM Interfacing with FPGA
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13K views • 2 years ago
26:14
VGA Interfacing with FPGA || explanation with working Verilog code
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10K views • 2 years ago
46:11
What is an IP in VLSI Design || Types of IP(soft,Hard,Firm IP) || How IP Licensing works
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8K views • 2 years ago
20:08
VLSI INTERVIEW QUESTIONS || RTL/ Digital Logic Design questions || Verilog & Digital logic questions
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21K views • 2 years ago
20:40
ASIC in VLSI Design || Types of ASIC
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12K views • 3 years ago
34:03
I2C Protocol Basics || Why I2C lines are OPEN DRAIN
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8.1K views • 3 years ago
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