3. Number of clock cycles taken when there is no forwarding circuitry

2. How many stalls are required in lw data dependency for 6 stage pipeline

1. Determining number of cycles in 6 stage pipeline

127. Determining Index | Tag | Byte Offset fields in Cache - Activity

126. Effects of increasing block size on Miss rate

125. How to find data block in memory and map it to a block in cache.

124. Example - How to calculate total bits in a Cache

123. Address subdivision and actual size of Cache in bits

122. Quick review of Memory Hierarchy and Cache

116. How to stall a cycle in load data hazards | Hazard Detection Unit

121. Tag and Valid bits in Cache with example

120. Basics of Cache and Direct Cache Mapping

119. Principal of Locality and Memory Hierarchy Levels

118. Introduction to Memory Hierarchy

117. Pipeline Hazards Detection and Handling - Activity

115. Revised MEM forwarding conditions for Double Data Hazards

114. Double Data Hazards

113. Forwarding Signals | Activity

112. Forwarding Path | Activity

111. Updated forwarding conditions for instructions to not write to registers | forwarding hardware.

110. Conditions to decide when and from which pipelines register to forward the data from.

109. Pipeline Control

108. How pipeline registers help writing the correct register value to memory in SW instructions.

107. Correct path to define destination register Rd

106. What are Pipeline Registers and why do we need them?

105. Which path causes the data and control hazards in pipeline architecture?

104. Branch Hazards

103. Solving Data Hazards with Code Reordering

102. Solving Data Hazards with Forwarding

101. Solving Data Hazard by Waiting | Stalling | Bubble