17:00
Flip flops | Excitation tables for SR, JK, D & T | STLD | Lec-123
149 views • 9 hours ago
16:12
Flip flops | Asynchronous inputs | STLD | Lec-122
193 views • 19 hours ago
15:15
flip flops | Characteristic equations | STLD | Lec-121
1K views • 2 weeks ago
11:55
T Flip flop | The edge triggered | STLD | Lec-120
395 views • 2 weeks ago
12:40
J K Flip flop | Edge triggered | STLD | Lec-119
317 views • 2 weeks ago
13:29
D flip flop | Edge Triggered | STLD| Lec-118
1.4K views • 1 month ago
16:19
S R Flip flop | Edge triggered | Waveforms | STLD | Lec-117
620 views • 1 month ago
13:12
D Latch | Gated | Truth Table | STLD | Lec-116
353 views • 1 month ago
18:58
SR latch | Gated | Truth Table | STLD | Lec-115
337 views • 1 month ago
16:19
S R Latch | NAND gate | STLD | Lec-114
834 views • 1 month ago
20:17
S R Latch | NOR gate | STLD | Lec-113
375 views • 1 month ago
13:03
Flip flops | Latches | STLD | Lec-112
332 views • 1 month ago
18:06
Sequential circuits | Classification | STLD | Lec-111
306 views • 1 month ago
11:01
PROM | Logic Diagram | Example problem | STLD | Lec-110
552 views • 2 months ago
21:47
PLA with PLA table | Example problem | STLD | Lec-109
303 views • 2 months ago
15:34
Design using PLA | STLD | Lec-108
260 views • 2 months ago
22:39
PAL with PAL table | Example problem | STLD | Lec-107
268 views • 2 months ago
15:01
Design using PAL | STLD | Lec-106
240 views • 2 months ago
15:21
Programmable Array Logic | PLA, PROM | STLD | Lec-105
263 views • 2 months ago
14:59
ROM | Types M-ROM, P-ROM, EPROM, EEPROM | STLD | Lec-104
258 views • 2 months ago
20:04
ROM | Programmable Logic Device | Part-2/2 | STLD | Lec-103
244 views • 2 months ago
16:14
Programmable Logic Device | Part-1/2 | STLD | Lec-102
295 views • 2 months ago
11:01
VHDL and Verilog codes | Differences VHDL & Verilog | Digital Design | Lec-18
518 views • 2 months ago
16:06
Component declaration and instantiation | VHDL | Digital Design | Lec-17
485 views • 2 months ago
12:28
Conditional and selected signal assignment statements | VHDL | Digital Design | Lec-16
332 views • 2 months ago
12:27
Concurrent signal assignment statement | Concurrent Vs Sequential | VHDL | Digital Design | Lec-15
380 views • 2 months ago
15:07
Process statement | Case, Null , Loop | Part-2/2 | Digital IC Design | Lec-13
413 views • 2 months ago
17:03
Process statement | Variable, Signal, Wait & If | Part-1/2 | Digital IC Design | Lec-13
342 views • 2 months ago
15:25
Operators in VHDL | Logical, Relational | Digital IC Design | Lec-12
300 views • 2 months ago
11:48
Data types | Pre-defined type & Scalar type | Part-2/2 | Digital IC Design | Lec-11
484 views • 2 months ago
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